1. Field of the Invention
The present invention generally relates to the field of digital signal processing. More particularly, the present invention relates to the field of analog to digital converters. In particular, the present invention relates to the field of analog to digital converters used mainly in a.c. signal conversion applications.
2. Description of the Prior Art
An analog-to-digital converter (hereafter referred as "ADC") is used in both a.c. and d.c. conversion applications. The ADCs are used to convert a.c. analog signals into digital output data, whereby a stable zero signal reference is desired to be maintained in the numeric output data over time and across temperature variations. Such applications include but are certainly not limited to digital audio.
Offset of the data stream (or digitized signal) produced by an ADC is the quantized numerical equivalent of an analog signal offset, and is an undesirable factor of error, especially if it drifts over time or temperature. Unavoidable data offset drift of an ADC results from the converter's intrinsic analog temperature coefficients which produce the net effect of a drifting conversion reference. It has been observed that even high grade ADC devices can produce a "center of data" drift equaling the magnitude of the third significant bit or greater over a reasonable operating temperature range. That is a relatively large amount of drift which must be eliminated for many applications.
Two prior art methods which have been widely used to cancel the output data offset of ADCs are digital highpass post-filtering and "auto zero" data offset compensation. Both methods have severe disadvantages in many potential applications for an ADC.
Digital highpass post-filtering requires a relatively complex digital signal processing (hereafter referred as "DSP") circuit added to the ADC, either internally as part of the integrated circuit or as an external support function. The cost of the additional post-filtering DSP may be prohibitive or there may occur other data errors due to DSP distortion. Additionally, the added conversion time introduced by the DSP post-filtering may limit the usefulness of this method.
Instead of DSP post-filtering, some presently available ADCs provide an internally programmed "auto zero" process to numerically subtract out the data offset. The disadvantage of this method is that it requires issuing a device instruction to the ADC which stops the converter flow for a period of time and puts the ADC through an offset cancellation procedure. Once the immediate data offset has been numerically subtracted from the data reference and the ADC is back into the operating mode, the data offset is subject to further drift. Frequent and timely operation of the auto zero function is therefore necessary to cancel the ADCs drifting output data offset. This option is simply not usable when continuous ADC operation is essential as for audio applications.
It is highly desirable to have a very efficient and also very effective design and construction of a novel offset canceling means to continuously cancel the output data offset of an ADC without interrupting the conversion flow. It is desirable to provide a novel offset canceling means which is relatively easy to design into new ADC devices, or easily applied as an external circuit to support existing ADCs. It is also desirable to provide a novel canceling means which is low in cost.